Serial ATA - It's Time to Get in Line Page 3
Ultra ATA-100 was the latest-generation Parallel ATA interface. With its maximum burst data transfer rate of 100 MB/sec, it superseded the Ultra ATA-66 interface. Before the industry completes its final transition to Serial ATA, Ultra ATA-100 is the last Parallel ATA interface.
Parallel ATA Interface Limitations
The Parallel ATA interface has a long history of design issues in spite of its success. Most of these issues have been successfully worked around, overcome, or simply ignored. They include:
- The 5-volt signaling requirement and high pin count (40-pin cable connectors)
- The 18-inch cable length limitation; cable width and cable routing problems
- Data robustness issues
5-Volt Signaling Requirement
Since the industry continues to reduce chip core voltages, Parallel ATA's 5-volt signaling requirement is increasingly difficult to meet. Parallel ATA has 26 5-volt signals per ATA channel, requiring the use of large physical chip pads to accommodate the high pin count. The large pads will ultimately dominate the chip as chip sizes are reduced.
18-Inch Cable Length Limitation
With the current Parallel ATA interface, the 18-inch cable length limitation can be a serious issue. The limited cable length complicates peripheral expansion choices, making some internal drive configurations impossible to implement. Of course, this depends on PC chassis size and the design and location of internal media bays.
The wide, flat ribbon cables of the Parallel ATA bus are difficult to route, and their shape and bulk can restrict air flow and create hot spots inside the chassis.
With Parallel ATA, data robustness has been a long-standing issue. During its early development, no form of data checking was designed into the Parallel ATA interface. However, a degree of data protection was added in the form of CRC, which enabled the verification of interface data, for the first time when the first UDMA mode was introduced. Unfortunately, ATA command data is still not checked and remains a potential error source.