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Reducing Lithography Size Hurts
Reducing lithography size brings the cells closer together, reducing the distance between the source and the drain. This allows more cells in a given space, hopefully reducing costs and allowing SSDs to have larger capacities. However, the one fundamental aspect that does not change with lithography size is the voltages that are applied to the cells. The 5V bias voltage has to be applied to bring the cells to a conductive state, you still need 0.5V to read a cell, and 20V to program/erase a cell. However, existing data corruption problems may actually get much worse because the EM fields are the same size and will be stronger in neighboring cells as they are closer together. This only makes the problem of possible data corruption worse.
Getting to larger densities may not be easily achieved because of this possible data corruption. Some sources indicate that the lower limit may be 20nm.
With increases in density, the probability of read disturbance increases as well. Overlaying this are the JEDEC requirements for data retention. The combination imposes some severe limits on the probability of data corruption, limiting today's SSD designs to approximately 20 nm.
Getting Out of the Lithography Pickle
While the title of this article is foreboding, and we are in trouble with respect to current SSD designs, developers are actively developing new techniques. In the immediate future all SSD's are likely to stick to the basic physics of floating-gate transistors. However, there are some additional techniques that can be used to reduce data corruption probabilities and improve data retention.
For example, engineers in Japan have found a way to isolate the particular cell in a line by applying 1V to the bit line connected to the cells that are not targeted. This should reduce write disturb problems (where the 20V program voltage disturbs neighboring cells even to the point of data corruption). This allows designers to make more dense chips and to also improve throughput.
Other options include the use of new materials, but these are so proprietary that they are almost non-existent.
A third option is to use a new physical phenomenon. For example, there is a new type of memory called carbon-resistive memory, but switching to a new storage technology has its own set of pitfalls.
Another way to improve density is to go beyond the MLC (Multi-Level Cell), which can store 2 bits per cell. This article details 3-bit and 4-bit cells being developed. These cells pose a challenge because voltage levels must be adjusted to read a particular bit in the cell without disturbing any of the others. But if this technology is successful, you can get more data with a given number of cells, increasing density and reducing costs. However, 3-bit cells have a much smaller number of program/erase cycles than others - around 1,000 cycles (MLC is typically around 10,000 and SLC is around 100,000).
It's fairly evident that SSDs using today's technology and techniques are pretty much stuck at 20-25nm. Anything smaller and the data protection and data corruption issues become so great that either the performance is abysmal, the data retention period doesn't meet JEDEC standards, or the cost increases.
There are efforts underway to develop new technologies that improve SSD performance and density and decrease costs (a big goal). However, these are fairly new techniques and are not likely to make it into devices for quite some time. Be forewarned – SSD development could easily stagnate at 20-25nm mark.
Jeff Layton is the Enterprise Technologist for HPC at Dell, Inc., and a regular writer of all things HPC and storage.
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